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A Heuristic (delta, D) Digraph to Interpolate between Hypercube and de Bruijn Topologies for Future On-Chip Interconnection Networks.
Samer Damaj
Thierry Goubier
Frédéric Blanc
Bernard Pottier
Published in:
ICPP Workshops (2009)
Keyphrases
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interconnection networks
fault tolerant
parallel algorithm
multistage
network on chip
routing algorithm
message passing
high speed
dynamic programming
parallel computers
optimal solution
routing protocol
low cost
anomaly detection
real time
probabilistic model
bayesian networks