A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic.
Salim FarahMagdy A. BayoumiPublished in: SoCC (2013)
Keyphrases
- low power
- power consumption
- clock gating
- power reduction
- logic circuits
- low cost
- high speed
- power dissipation
- delay insensitive
- single chip
- power saving
- vlsi architecture
- digital signal processing
- energy efficiency
- cmos technology
- low power consumption
- vlsi circuits
- gate array
- energy saving
- image sensor
- efficient implementation
- computer systems
- mixed signal
- signal processing