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Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications.
Zheng Liang
Juha Plosila
Lu Yan
Kaisa Sere
Published in:
PDCAT (2006)
Keyphrases
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low power
network on chip
power dissipation
cmos technology
power consumption
low cost
high speed
single chip
multi processor
digital signal processing
parallel implementation
image sensor
routing algorithm
efficient implementation
object oriented
real time
ultra low power
data transfer
network simulator