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A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology.
Naveen Kumar Kancharapu
Marshnil Vipin Dave
Veerraju Masimukkula
Maryam Shojaei Baghini
Dinesh Kumar Sharma
Published in:
ISVLSI (2011)
Keyphrases
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cmos technology
low power
power consumption
low voltage
high speed
distribution network
low cost
low power consumption
single chip
power dissipation
mixed signal
digital signal processing
power management
parallel processing
nm technology
ant colony algorithm
data center
frame rate
power reduction
traveling salesman problem
silicon on insulator
real time
cmos image sensor