A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology.
Naveen Kumar KancharapuMarshnil Vipin DaveVeerraju MasimukkulaMaryam Shojaei BaghiniDinesh Kumar SharmaPublished in: ISVLSI (2011)
Keyphrases
- cmos technology
- low power
- power consumption
- low voltage
- high speed
- distribution network
- low cost
- low power consumption
- single chip
- power dissipation
- mixed signal
- digital signal processing
- power management
- parallel processing
- nm technology
- ant colony algorithm
- data center
- frame rate
- power reduction
- traveling salesman problem
- silicon on insulator
- real time
- cmos image sensor