Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz.
Stanley SchusterPeter W. CookPublished in: IEEE J. Solid State Circuits (2003)
Keyphrases
- low power
- high speed
- delay insensitive
- power consumption
- asynchronous communication
- vlsi circuits
- cmos technology
- logic circuits
- low cost
- power dissipation
- power reduction
- mixed signal
- shift register
- single chip
- high power
- asynchronous circuits
- image sensor
- vlsi architecture
- digital signal processing
- wireless transmission
- low power consumption
- real time
- image processing