An integrated MOS transistor associative memory system with 100 ns cycle time.

Ryo Igarashi Toru Yaita

Published in: AFIPS Spring Joint Computing Conference (1967)

Keyphrases

associative memory
storage capacity
floating gate
kohonen feature map
bi directional
high speed
alpha beta
neural network
integrated circuit
wireless sensor networks
auto associative
low power
routing protocol
human memory
ad hoc networks
knn
feature selection
data sets