A high speed BiCMOS tristate buffer circuit.

Chatpong Suriyaammaranon Kobchai Dejhan Fusak Cheevasuvit Chatcharin Soonyeekan

Published in: ICECS (1999)

Keyphrases

database
high speed
low power
real time
mixed signal
frame rate
shift register
data structure
buffer size
virtual memory
buffer allocation
neural network