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A seamless representation for coupling transistor sizing with nanometric CMOS layout generation.
Stephanie Youssef
Farakh Javid
Damien Dupuis
Ramy Iskander
Marie-Minerve Louërat
Published in:
ECCTD (2011)
Keyphrases
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high speed
low power
circuit design
analog vlsi
image processing
case study
image representation
power consumption
web pages
website
image sequences
low cost
generation method
spatial layout