A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS.
Liu WangGuojing YeYumei HuangPublished in: ASICON (2021)
Keyphrases
- low power
- cmos technology
- mixed signal
- phase locked loop
- low voltage
- high resolution
- analog to digital converter
- power consumption
- high voltage
- low cost
- high speed
- nm technology
- vlsi circuits
- user friendly
- metal oxide semiconductor
- single chip
- image sensor
- cmos image sensor
- data conversion
- high power
- low power consumption
- image processing
- high frequency
- vlsi architecture
- power reduction
- multi channel
- super resolution
- digital signal processing
- delay insensitive
- gate array
- logic circuits
- parallel processing
- power management
- imaging systems
- operating conditions
- wide dynamic range
- silicon on insulator
- real time