) for High Speed Cryptographic Processors.
Soonhak KwonChang Hoon KimChun Pyo HongPublished in: ICCSA (4) (2004)
Keyphrases
- high speed
- parallel algorithm
- low power
- smart card
- parallel processing
- single processor
- hash functions
- parallel processors
- single chip
- embedded processors
- high speed networks
- parallel computing
- real time
- security protocols
- encryption scheme
- multiprocessor systems
- s box
- secure communication
- shared memory
- communication delays
- memory subsystem
- list scheduling