Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation.

Jaco Hofmann Amir Zjajo Carlo Galuzzi René van Leuken

Published in: EMBC (2016)

Keyphrases

massive scale
design methodology
high speed
data flow
vlsi implementation
real time
low cost
analog vlsi
low latency
database machine
software architecture
host computer
chip design
hardware software
associative memory
neural network
level parallelism