A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec.
Sanghoon KwakJinwook KimDongsoo HarPublished in: IEICE Trans. Inf. Syst. (2008)
Keyphrases
- hardware architecture
- intra coding
- video codec
- video coding
- coding method
- bitstream
- intra frame
- bit rate
- prediction scheme
- video coding standard
- hardware implementation
- rate distortion
- block matching motion estimation
- inter frame
- macroblock
- distributed video coding
- motion estimation
- coding scheme
- motion compensation
- hardware architectures
- video quality
- video compression
- error resilience
- motion compensated
- transform domain
- low bit rate
- low complexity
- video decoder
- rate control
- residual signal
- coding efficiency
- motion vectors
- intra prediction
- neural network
- associative memory
- error concealment
- bit allocation
- scalable video coding
- field programmable gate array
- machine learning
- compressed domain
- compression ratio
- signal processing
- computational complexity
- pattern recognition
- image processing
- motion jpeg
- computer vision
- wyner ziv
- variable block size