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Architectural exploration of a fine-grained 3D cache for high performance in a manycore context.
Eric Guthmuller
Ivan Miro Panades
Alain Greiner
Published in:
VLSI-SoC (2013)
Keyphrases
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fine grained
coarse grained
access control
tightly coupled
massively parallel
user intent
embedded processors
data lineage
data model
data access