Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA.

Chi-Chia Sun Jürgen Götze Hong-Yuan Jheng Shanq-Jang Ruan

Published in: CIT (2010)

Keyphrases

sparse matrix
network on chip
floating point
routing algorithm
network simulator
multi processor
data transfer
low cost
random projections
hardware design
single chip
field programmable gate array
power dissipation