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Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design.

Francesco SgherziAlberto ParraviciniMarco SiracusaMarco D. Santambrogio
Published in: FCCM (2021)
Keyphrases
  • real time
  • case study
  • high speed
  • user interface
  • query processing
  • random walk
  • directed graph
  • hardware design
  • low cost
  • graph model
  • memory space
  • single chip
  • programmable logic
  • hardware description language
  • verilog hdl