A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS.

Ran Li Qi Zhao Ting Yi Zhiliang Hong

Published in: ASICON (2011)

Keyphrases

power consumption
clock gating
nm technology
low power
high speed
random access memory
power dissipation
cmos technology
power reduction
power management
database
metal oxide semiconductor
max csp
design considerations
real time
vlsi circuits