A Real-Time and Parametric Parallel Video Compression Architecture Using FPGA.
Cássio Alves CarneiroFrancisco M. P. GarciaFlávia M. FreitasZélia M. A. PeixotoAmanda R. M. DinizAbraham AlcaimPublished in: ISPA Workshops (2006)
Keyphrases
- video compression
- pipelined architecture
- real time
- motion compensation
- video processing
- hardware implementation
- motion estimation
- video coding
- dedicated hardware
- field programmable gate array
- fpga implementation
- video data
- motion compensated
- video conferencing
- parallel architecture
- fpga technology
- low bit rate
- image and video compression
- fpga device
- low cost
- fpga hardware
- real time video processing
- compression ratio
- bit allocation
- high speed
- hardware architecture
- rate distortion
- xilinx virtex
- low power consumption
- parallel processing
- distributed video coding
- video codec
- parallel hardware
- video decoder
- signal processing
- computer vision
- embedded systems
- vision system
- hardware design
- image data