High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and g/I Methodology.
Chen ChenHongyi WangXinyue SongFeng LiangKaikai WuTao TaoPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2022)
Keyphrases
- integrated circuit
- high dimensional
- optimization problems
- data points
- optimization algorithm
- pattern recognition
- bayesian networks
- low dimensional
- high dimensionality
- optimization method
- dimensionality reduction
- nearest neighbor
- variable selection
- feature space
- high dimensional data
- probability distribution
- posterior distribution
- efficient optimization
- hardware description language