An alternative logic approach to implement high-speed low-power full adder cells.

Mariano Aguirre Mónico Linares Aranda

Published in: SBCCI (2005)

Keyphrases

low power
logic circuits
high speed
low cost
power consumption
power dissipation
digital signal processing
single chip
wireless transmission
delay insensitive
high power
vlsi architecture
gate array
mixed signal
frame rate
vlsi circuits
cmos technology
video sequences
real time