Synthesis and optimization of asynchronous dual rail encoded circuits based on partial acknowledgement.
Yu ZhouChun ShiZhengjie DengAlex YakovlevPublished in: ASICON (2017)
Keyphrases
- high speed
- delay insensitive
- analog circuits
- high level synthesis
- optimization problems
- optimization algorithm
- logic synthesis
- design space exploration
- asynchronous circuits
- shift register
- global optimization
- constrained optimization
- optimization process
- low power
- optimization model
- real time
- program synthesis
- convex optimization
- search space
- artificial neural networks