Using model checking to derive loop bounds of general loops within ANSI-C applications for measurement based WCET analysis.
Bernhard RiederPeter P. PuschnerIngomar WenzelPublished in: WISES (2008)
Keyphrases
- model checking
- temporal logic
- temporal properties
- lower bound
- formal verification
- symbolic model checking
- abstract interpretation
- formal specification
- finite state
- automated verification
- verification method
- computation tree logic
- transition systems
- asynchronous circuits
- formal methods
- static analysis
- finite state machines
- distributed systems