A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.
Theepan MoorthyAndy YePublished in: FPL (2008)
Keyphrases
- fpga technology
- field programmable gate array
- digital signal processors
- hardware implementation
- hardware architecture
- hardware design
- pipelined architecture
- host computer
- hardware software
- hardware software co design
- processing elements
- parallel architecture
- reconfigurable hardware
- parallel computing
- associative memory
- embedded systems
- image processing algorithms
- fpga device
- pattern recognition
- hardware and software
- real time
- massively parallel
- graphical models
- variable block size motion estimation