A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding.
Sinan YalcinHasan F. AtesIlker HamzaogluPublished in: FPL (2005)
Keyphrases
- video coding
- motion vectors
- motion estimation algorithm
- hardware architecture
- block matching motion estimation
- motion compensation
- motion estimation
- low bit rate video coding
- bit rate
- motion compensated
- video sequences
- video compression
- rate distortion
- motion field
- macroblock
- hardware implementation
- block matching
- computational complexity
- video data
- video quality
- reference frame
- video codec
- error concealment
- high definition
- rate control
- field programmable gate array
- block size
- prediction error
- video coder
- coding method
- associative memory
- advanced video coding
- video frames
- image sequences
- bit allocation
- multi layer
- frame rate
- bitstream