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A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS.
Remco C. H. van de Beek
Cicero S. Vaucher
Domine M. W. Leenaerts
Eric A. M. Klumperink
Bram Nauta
Published in:
IEEE J. Solid State Circuits (2004)
Keyphrases
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high speed
power consumption
low cost
low power
packet loss
analog vlsi
real time
motion estimation
floating point