A Computationally Efficient, Hardware Re-configurable Architecture for QRS Detection and ECG authentication.
Weihong YanYuxin JiCe MaLining HuYang ZhaoYongfu LiGuoxing WangYong LianPublished in: A-SSCC (2021)
Keyphrases
- computationally efficient
- ecg signals
- hardware architecture
- real time
- vlsi implementation
- mit bih arrhythmia database
- vlsi architecture
- heart rate variability
- hardware implementation
- software implementation
- detection algorithm
- pipeline architecture
- low cost
- detection rate
- false alarms
- hardware software
- hardware design
- management system
- detection method
- automatic detection
- hardware and software
- anomaly detection
- heart rate
- dedicated hardware
- hardware architectures
- content addressable
- software architecture
- image processing
- user authentication
- commercial off the shelf
- parallel architecture
- computing platform
- beat classification
- computer systems