A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.
Shiwei ZhangWei DengHaikun JiaHongzhuo LiuShiyan SunPingda GuanBaoyong ChiPublished in: CICC (2023)