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A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.

Shiwei ZhangWei DengHaikun JiaHongzhuo LiuShiyan SunPingda GuanBaoyong Chi
Published in: CICC (2023)
Keyphrases
  • high speed
  • low power
  • cmos technology
  • nm technology
  • high frequency
  • power consumption
  • feature vectors
  • frame rate
  • low cost
  • frequency band