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A maximum time difference pipelined arithmetic unit based on CMOS gate array.

Zhimin TangPeisu Xia
Published in: J. Comput. Sci. Technol. (1995)
Keyphrases
  • gate array
  • low power
  • power consumption
  • high speed
  • low cost
  • logic circuits
  • cmos technology
  • vlsi circuits
  • power supply
  • delay insensitive
  • analog vlsi
  • single chip
  • power dissipation
  • control unit
  • data flow
  • image sensor