Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA.
Khalid Al-HussainiBorhanuddin Mohd AliPooria VarahramShaiful J. HashimRonan FarrellPublished in: Int. J. Wirel. Mob. Comput. (2017)
Keyphrases
- low complexity
- wireless video
- vlsi architecture
- video coding scheme
- low cost
- hardware implementation
- field programmable gate array
- video encoder
- multiple description coding
- hardware architecture
- real time
- motion estimation
- hardware software
- computational complexity
- ofdm system
- distributed video coding
- bit plane
- vlsi implementation
- lower complexity
- high speed
- analytical model
- embedded systems
- mimo systems
- wyner ziv
- video streaming
- orthogonal frequency division multiplexing
- coding scheme