USB 3.0 Using FPGA Optimization for 8b/10b Encoder/Decoder.
Chun-Yu SuChiung-An ChenShih-Lun ChenJin-Yang LaiPublished in: ISPACS (2021)
Keyphrases
- successive approximation
- low complexity
- video codec
- decoding process
- distributed video coding
- fpga implementation
- noisy channel
- video coding scheme
- rate distortion
- error control
- high speed
- power reduction
- vector quantization
- wyner ziv
- motion estimation
- field programmable gate array
- hardware implementation
- bit rate
- signal processing
- low cost
- rate allocation
- hardware architecture
- transform domain
- video compression
- smart card
- image quality
- mpeg avc
- distributed source coding
- video decoder