Low-power hardware implementation of SNN with decision block for recognition tasks.
Luis A. Camuñas-MesaBernabé Linares-BarrancoTeresa Serrano-GotarredonaPublished in: ICECS (2019)
Keyphrases
- low power
- hardware implementation
- low cost
- high speed
- power consumption
- signal processing
- software implementation
- efficient implementation
- fractal encoding
- image processing algorithms
- single chip
- field programmable gate array
- digital signal processing
- low power consumption
- vlsi architecture
- vlsi circuits
- logic circuits
- image processing
- computer vision
- power dissipation
- pipelined architecture
- gate array
- image compression