Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS.
Arthur Lombardi CamposJoão NavarroMaximiliam LuppePublished in: SBCCI (2019)
Keyphrases
- low power
- analog to digital converter
- single chip
- cmos technology
- nm technology
- power consumption
- low cost
- high speed
- mixed signal
- power dissipation
- low power consumption
- image sensor
- logic circuits
- vlsi architecture
- cmos image sensor
- digital signal processing
- delay insensitive
- ultra low power
- vlsi circuits
- high power
- gate array
- multi channel
- power reduction
- wireless transmission
- shift register
- low voltage
- power saving
- metal oxide semiconductor