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RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures.
Venkata Yaswanth Raparti
Sudeep Pasricha
Published in:
IEEE Trans. Multi Scale Comput. Syst. (2018)
Keyphrases
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heterogeneous computing
memory usage
compute intensive
memory requirements
memory management
network on chip
memory bandwidth
low latency
digital signal processors
memory hierarchy
multi processor
data transfer
routing algorithm
computing power
prefetching
operating system
response time