A 1.2-V, 1.8-GHz low-power PLL using a class-F VCO for driving 900-MHz SRD band SC-circuits.
Tim SchumacherMarkus StadelmayerThomas FasethHarald PretlPublished in: ISLPED (2020)
Keyphrases
- low power
- high speed
- cmos technology
- power consumption
- logic circuits
- vlsi circuits
- low cost
- single chip
- high power
- digital signal processing
- power dissipation
- power reduction
- delay insensitive
- low power consumption
- vlsi architecture
- wireless transmission
- real time
- nm technology
- low voltage
- clock frequency
- high frequency
- image processing