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NoC-aware cache design for multithreaded execution on tiled chip multiprocessors.
Ahmed Abousamra
Alex K. Jones
Rami G. Melhem
Published in:
HiPEAC (2011)
Keyphrases
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multithreading
parallel computing
design process
highly efficient
circuit design
chip design
high speed
data access
embedded systems
single chip
network on chip