Login / Signup

A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery.

Li WangZhao ZhangC. Patrick Yue
Published in: VLSI Circuits (2021)
Keyphrases