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An efficient hardware design of SIFT algorithm using fault tolerant reversible logic.

Chandrajit PalPabitra DasSudhindu Bikash MandalAmlan ChakrabartiSamik BasuRanjan Ghosh
Published in: ReTIS (2015)
Keyphrases
  • fault tolerant
  • hardware implementation
  • distributed systems
  • fault tolerance
  • hardware design
  • artificial intelligence
  • np hard
  • scheduling problem
  • fine grained