Low-power macro-cells for pulse code arithmetic.

Sigbjørn Næss Tor Sverre Lande

Published in: ICECS (1998)

Keyphrases

low power
power consumption
low cost
high speed
single chip
source code
high power
vlsi circuits
wireless transmission
low power consumption
vlsi architecture
cmos technology
gate array
real time
signal processor
power saving
delay insensitive
logic circuits
low density parity check
data flow
computer simulation