A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme.
Shuenn-Yuh LeeChia-Chyang ChenShyh-Chyang LeeChih-Jen ChengPublished in: ISCAS (2006)
Keyphrases
- vlsi architecture
- low power
- high speed
- power consumption
- vlsi implementation
- control scheme
- low cost
- dynamic programming
- low complexity
- real time
- parallel processing
- neural network
- parallel architecture
- shared memory
- computational complexity
- dynamic model
- parallel algorithm
- rate distortion
- markov random field
- control system
- image sequences