Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.
Toshimasa NamekawaShinji MiyanoRyo FukudaRyo HagaOsamu WadaHironori BanbaSatoru TakedaKazuhiro SudaKenichiro MimotoSatoshi YamaguchiTsutomu OhkuboHiroshi TakatoKenji NumataPublished in: IEEE J. Solid State Circuits (2000)