A 4X4-block level pipeline and bandwidth optimized motion compensation hardware design for H.264/AVC decoder.
De-Yuan ShenTsung-Han TsaiPublished in: ICME (2009)
Keyphrases
- motion compensation
- hardware design
- video coding standard
- video codec
- video coding
- motion compensated prediction
- motion compensated
- video compression
- motion vectors
- motion estimation
- hardware implementation
- video quality
- video coder
- compression efficiency
- variable block size
- rate distortion
- macroblock
- video streaming
- block matching
- error concealment
- intra frame
- bit rate
- motion field
- intra prediction
- distributed video coding
- coding efficiency
- low complexity
- rate distortion optimized
- scalable video coding
- rate control
- mode decision
- real time
- deblocking filter
- field programmable gate array
- coding method
- digital video
- reference frame
- compressed video
- low bit rate
- error resilience
- wyner ziv
- transform domain
- video encoder
- prediction error
- mode selection
- optical flow
- computational complexity
- computer vision