Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions.
P. Vijay SumanParitosh K. PandyaPublished in: LATA (2009)
Keyphrases
- timed automata
- model checking
- reachability analysis
- theorem prover
- expressive power
- first order logic
- theorem proving
- real time systems
- databases
- floating point
- lower bound
- information retrieval
- predictive state representations
- inference rules
- artificial intelligence
- state transition
- learning algorithm
- state transitions
- real time