Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style.
Vahid ForoutanMohammadReza TaheriKeivan NaviArash Azizi MazreahPublished in: Integr. (2014)
Keyphrases
- low power
- logic circuits
- power consumption
- power dissipation
- single chip
- low cost
- high speed
- low power consumption
- cmos technology
- vlsi architecture
- gate array
- digital signal processing
- wireless transmission
- ultra low power
- vlsi circuits
- chip design
- high power
- delay insensitive
- mixed signal
- image sensor
- nm technology
- power reduction
- circuit design
- cmos image sensor
- analog to digital converter
- real time