A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC.
Akira TanabeYasushi NakaharaAkio FurukawaTohru MogamiPublished in: IEEE J. Solid State Circuits (2003)
Keyphrases
- multi valued
- delay insensitive
- high speed
- random access memory
- integrated circuit
- chip design
- logic programming
- asynchronous circuits
- classical logic
- low cost
- single valued
- circuit design
- low power
- predicate logic
- deontic logic
- automated reasoning
- truth values
- soft constraints
- linear logic
- low voltage
- probability theory
- databases
- hd video