A low power and low area active clock deskewing technique for sub-90nm technologies.

Ashok Narasimhan Ramalingam Sridhar

Published in: SoCC (2008)

Keyphrases

low power
power consumption
high speed
low power consumption
cmos technology
low cost
nm technology
power reduction
single chip
high power
logic circuits
power saving
vlsi architecture
wireless transmission
digital signal processing
delay insensitive
low voltage
mixed signal
vlsi circuits
ultra low power