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90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation.
Anisha Ramesh
Si-Young Park
Paul R. Berger
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2011)
Keyphrases
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read write
write operations
random access memory
access control
random access
hard disk
neural network
wireless sensor networks
data management
wireless networks
memory access