Scalable parallel simulation of networks on chip.

Marcus Eggenberger Martin Radetzki

Published in: NOCS (2013)

Keyphrases

packet switched
network on chip
high speed
low cost
parallel processing

parallel computers
mathematical model
parallel implementation
distributed memory
physical design

computer architecture
simulation model
network structure
parallel computing
shared memory

multithreading
multi processor
analog vlsi
asynchronous cellular automata
complex networks