Hardware accelerator for high accuracy sign language recognition with residual network based on FPGAs.
Dong YangJianwu LiGuocun HaoQirui ChenXi WeiZirui DaiZixian HouLei ZhangXiaoran LiPublished in: IEICE Electron. Express (2024)
Keyphrases
- sign language recognition
- field programmable gate array
- high accuracy
- hardware implementation
- embedded systems
- sign language
- gesture recognition
- parallel computing
- image processing algorithms
- hardware software
- fpga technology
- massively parallel
- computing systems
- reconfigurable hardware
- parallel architectures
- hand tracking
- low cost
- hardware and software
- image sequences
- real time