Visual-Trace Simulation of Concurrent Finite-State Machines for Validation and Model-Checking of Complex Behaviour.
Robert ColemanVladimir Estivill-CastroRené HexelCarl LustyPublished in: SIMPAR (2012)
Keyphrases
- model checking
- finite state machines
- temporal logic
- formal verification
- model checker
- temporal properties
- formal specification
- finite state
- symbolic model checking
- automated verification
- reachability analysis
- verification method
- epistemic logic
- formal methods
- pspace complete
- finite state automata
- computation tree logic
- timed automata
- transition systems
- high level
- asynchronous circuits
- process algebra
- bounded model checking
- software engineering
- database