A Hardware Implementation of a Dynamically Adjustable Block-based Neural Network.
Shaoyu LiuGregory D. PetersonSeong G. KongPublished in: ERSA (2005)
Keyphrases
- hardware implementation
- neural network
- efficient implementation
- fpga implementation
- signal processing
- hardware design
- software implementation
- artificial neural networks
- back propagation
- image processing algorithms
- dedicated hardware
- hardware architecture
- field programmable gate array
- pipeline architecture
- block size
- neural network model
- fractal image compression
- memory management
- image binarization
- fpga technology
- pattern recognition
- motion compensation
- parallel architecture
- software development
- low cost
- multiresolution