Reduction of Parasitic Capacitance Impact in Low-Power SAR ADC.
Chenglong ZhangHaibo WangPublished in: IEEE Trans. Instrum. Meas. (2012)
Keyphrases
- low power
- high speed
- single chip
- low cost
- power consumption
- power reduction
- high power
- synthetic aperture radar
- low power consumption
- vlsi circuits
- digital signal processing
- power dissipation
- wireless transmission
- vlsi architecture
- logic circuits
- analog to digital converter
- sar images
- real time
- mixed signal
- delay insensitive
- cmos technology
- gate array